Clock signals are used by a wide variety of digital circuits to control the timing of various events occurring during the operation of the digital circuits. For example, clock signals are used to designate when command signals, data signals, and other signals used in memory devices and other computer components are valid and can thus be used to control the operation of the memory device or computer system. For instance, a clock signal can be used to develop sequential column addresses when an SDRAM is operating in burst mode.
Generating a signal using a clocked signal as an input can be difficult to coordinate. Some of the signals generated may need to be timed to either a rising or falling edge of a clock signal, or may become operative only after a given number of clock cycles. Many circuits have been created to coordinate these signals with clock signals, with varying degrees of success. One of the problems with generating signals from a clock signal is a time delay caused by additional circuitry needed for the coordination. Each component used in a circuit (logic gate, buffer, amplifier, etc.) introduces a time delay when producing a signal. Capacitive loading, internal resistance, and other factors cause this delay. To keep the delay caused by additional components to a minimum, circuits using a clocked signal to help generate other signals should be made with as few components as necessary. As memory speeds, bus speeds, and processor speeds increase, it becomes even more important to minimize or eliminate delays in clocked signal generation circuits.
An example of a circuit that uses a clocked signal as an input to generate other signals is shown in FIG. 1. A signal generation circuit 10 includes a NAND gate 40 receiving a clock input signal CLK from a circuit input terminal 20. The NAND gate 40 also receives an inverted, delayed clock signal IDCLK that is produced by coupling the clock signal CLK through an inverter 32 and a delay circuit 34. To be operational, the NAND gate 40 requires a logic 0 or LOW signal to be asserted at an inverted enable input 46. In conventional circuits, the LOW signal is typically at 0 volts and the HIGH signal is at 5 volts, 3.3 volts or some other voltage, depending on the circuit. A column signal COL is received at a circuit input terminal 22 and then inverted at an inverter 36. A HIGH COL signal coupled through the inverter 36 enables the NAND gate 40. As further discussed below, there is a delay time between the times when the signal is received at the input of a logic gate and when the signal is produced at the output of the logic gate.
The signal generation circuit 10 produces an Input/Output pull-up, or IOPU signal at a circuit output terminal 60 based on the CLK, IDCLK and COL signals. When the clock signal CLK goes HIGH, the output of the delay circuit 34 remains HIGH for a short delay period, thereby causing the NAND gate 40 to output a LOW pulse signal P1. After the delay of the delay circuit 34, the output of the delay circuit goes LOW, thereby causing the output of the NAND gate 40 to go HIGH, thereby terminating the pulse signal P1. The pulse signal P1 generated at the NAND gate output is delayed by a delay circuit 52 and then inverted three times at inverters 54, 56, and 58, respectively. The IOPU signal generated by the inverter 58 is coupled to the circuit output terminal 60. This signal is used in a data path of a memory circuit to restore I/O lines to a desired voltage between data access cycles.
The operation of the signal generating circuit 10 will be described with reference to the timing diagram of FIG. 2. Assuming, for illustration, that the COL signal is always in a HIGH state, generating the pulse signal P1 is controlled only by the CLK and IDCLK signals received at the NAND gate 40. Before the time t0, the CLK signal has been at a LOW state for some time period; IDCLK will be HIGH by virtue of the inverter 32. Since the NAND gate 40 has one LOW and one HIGH input, the output of the NAND gate 40 is also HIGH, shown as trace P1 in FIG. 2. At time t0, the CLK signal changes from the LOW state to a HIGH state. As stated above, because of capacitance, resistance, and other factors within a logic device, there is a delay between the time a signal is presented on the input to the logic device and when a signal is generated at the output of the logic device. This propagation delay can vary from one logic device to another based on such factors as the number of inputs, the size of transistors within the logic gates and other factors. For convenience, one standard propagation delay period for all logic devices is assumed.
Immediately after the CLK switches from a LOW to HIGH at time t0, the signal received at the NAND gate 40 also changes to HIGH. As explained below, the other NAND gate 40 input still retains the HIGH signal it was receiving prior to the time the clock signal changed. Since both inputs are HIGH, the NAND gate 40 will generate a LOW output signal. Howvever, due to the logic gate propagation delay of the NAND gate 40, the pulse signal P1 remains HIGH until time t1. At time t1, the logic gate propagation delay has elapsed and the pulse signal P1 falls from HIGH to LOW. This logic gate propagation delay for the NAND gate 40 is shown on the P1 trace, labeled as Igpd40.
After the rising CLK edge at time t0, the CLK signal begins propagating through the inverter 32 and the delay circuit 341 to generate the IDCLK signal. First, a logic gate propagation delay exists when passing through the inverter 32. Next, the inverted CLK signal is delayed by the delay circuit 34, which has been added to postpone the CLK signal change. The time delay of delay circuit 34 is determined by the design engineer and built into the integrated circuit. This delay will ultimately select the length of the pulse signal P1. The logic gate propagation delay caused by the inverter 32 is shown as Igpd32 on trace IDCLK, while the time delay due to the delay circuit 34 is shown as td34. Once the CLK signal has passed through the inverter 32 and the delay circuit 34 at time t5, the IDCLK signal changes from HIGH to LOW. When IDCLK falls to a LOW signal at time t5, the NAND gate 40 has one HIGH input and one LOW input. This causes the NAND gate 40 to output a HIGH signal. Following another logic gate propagation delay for the NAND gate 40, the pulse signal P1 is pulled HIGH and the pulse is complete. This second propagation delay is also shown on trace P1.
The pulse signal P1 created at the output of the NAND gate 40 is deficient for use as an IOPU. First, the pulse signal P1 is a negative pulse beginning HIGH, falling LOW and then pulled back HIGH. The IOPU signal requires the opposite orientation. Second, the output pulse signal P1 lacks the driving capability needed by the circuit. The low driving capacity pulse signal P1 has a relatively shallow slope when compared to the steep slope of the high driving capacity CLK signal. Because of these deficiencies, the output pulse signal P1 must be inverted and buffered before it can be used as an IOPU signal.
After the pulse signal P1 is generated by the NAND gate 40, the delay circuit 52 delays it. This delay circuit is necessary to coordinate the IOPU signal with other signals generated in the signal generating, circuit 10, for instance, CDEn at a circuit output terminal 62 and CDE.sub.-- R at a circuit output terminal 64. These other signals are generated within the signal generating circuit 10 by circuitry generally labeled as 50. The added delay from the delay circuit 52 is shown in FIG. 2 on the I1 trace. The trace for I1 parallels trace P1, except that I1 trails the P1 trace by the time delay created by the delay circuit 52.
The signal I1 next propagates to the inverter 54, the output of which is shown as trace I2 in FIG. 2. The signal I2 output by the inverter 54 is inverted compared to the signal I1. The trace for I2 also differs from that of I1 in that it trails by another logic gate propagation delay ascribed to the inverter 54, labeled as Igpd54. The inverter 54 also buffers the signal, seen by the sharper pull-up curves from LOW to HIGH beginning at time t3. The signal I2 has the correct orientation to become the IOPU signal, but still lacks enough drive capacity. A convenient way to buffer a signal while retaining its original orientation is to pass the signal through two inverter circuits. The signal I2 is then propagated to inverter 56 shown as trace I3. Following the logic gate propagation delay for the inverter 56 shown on trace I3, the signal is again inverted and buffered. Finally, the signal I3 is propagated through the inverter 58, shown as a trace IOPU. Again, after the standard logic gate propagation delay for inverter 58, the signal is inverted and buffered. The signal IOPU at circuit output terminal 60 has the desired orientation and has sufficient driving power to be used as the Input/Output pull-up signal.
Given today's demand for faster memory circuits, there is a need to develop signal generation circuitry which can generate an IOPU signal of the correct orientation and drive capacity with fewer delays due to logic gates than the current state of the art.